/*******************************************************************
* Copyright (C) 2022 Xilinx, Inc. All Rights Reserved.
* Copyright (C) 2022 - 2024 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xsdps.h"

/*
* The configuration table for devices
*/

XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
{
	{
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_DEVICE_ID,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_BASEADDR,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_SDIO_CLK_FREQ_HZ,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_HAS_CD,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_HAS_WP,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_BUS_WIDTH,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_MIO_BANK,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_HAS_EMIO,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_SLOT_TYPE,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_IS_CACHE_COHERENT,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_CLK_50_SDR_ITAP_DLY,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_CLK_50_SDR_OTAP_DLY,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_CLK_50_DDR_ITAP_DLY,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_CLK_50_DDR_OTAP_DLY,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_CLK_100_SDR_OTAP_DLY,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_CLK_200_SDR_OTAP_DLY,
		XPAR_VERSAL_CIPS_0_PSPMC_0_PSV_PMC_SD_1_CLK_200_DDR_OTAP_DLY
	}
};
